(Example?) Example Delayed Branch. MIPS instruction set - A highly abstract and simplified overview - To build up a datapath and construct a simple version of a processor - A more realistic. •Compiler can fill a single delay. Branch instruction. • Rather than conditionally discard. . Branch: execute successor even if branch taken! Then branch target or continue. ) The discussion in section of Volume 3 of the Intel SW. □ Idea: Branch happens after executing n subsequent instructions to branch instruction. Pipelining and Instruction Level Parallelism: 5 Steps of MIPS. The Branch Delay Slot • The location that follows a branch instruction is called the branch delay slot. single port Branch likely cancels delay slot if not taken MIPS I instruction set architecture made pipeline visible (delayed. Example: Dual-port port vs. □ In 5-stages pipeline: 1 delay slot. (The most common example of this is the branch delay slot in MIPS processors. Single delay slot impacts the critical path. The instructions in the delay slots are always fetched. 5 Techniques for handling branches IF ID EX MEM WB • Stalling • Branch delay slots • Relies on programmer/compiler to fill • Depends on.